1. Field of the Invention
The present invention relates to a variable dividing circuit capable of varying the number of dividing in a semiconductor integrated circuit, and particularly, the present invention relates to a variable dividing circuit effective for a circuit having many divided stages and requiring the high-speed operation.
2. Description of the Related Art
A conventional variable dividing circuit is configured by a down counter with a data loading function, and a desired number of dividing is realized by loading a predetermined value when the all data of each bit of the counter becomes logical “0” (a “L” level). For example, a variable dividing circuit using a counter is disclosed in JP-A-6-91425.
The above-described conventional variable dividing circuit involves a problem such that the operational speed thereof is low because a flip-flop configuring a counter in the conventional variable dividing circuit has a data loading function. For example, the highest operational speed of a flip-flop without a data loading function (for example, a D-type flip-flop with a resetting function) is 1.667 GHz, on the contrary, the highest operational speed of the flip-flop with the data loading function is 1.25 GHz.